Display systems for electronic data processing equipment

ABSTRACT

A display system for electronic data storage and retrieval equipment which permits the consecutive and intermittent display of information through a plurality of radiation active elements, such as cold cathode display tubes. The display system includes a recirculating main shift register which may form part of the data storage and retrieval equipment and which main shift register receives data bits representing characters to be displayed. A recirculating anode shift register is connected to the main shift register through a pulse divider and also receiver bits representing certain of the characters to be displayed. An anode driving circuit comprised of a plurality of anode drivers is operated in conjunction with the anode shift register and a plurality of cathode drivers are operated by a decoder connected to the main shift register. In this way a selected anode driver is energizable together with a cathode driver which will energize a selected one of said display tubes.

United States Patent [191 Abrams et a1.

[11] 3,820,080 1 June 25, 1974 1 1 DISPLAY SYSTEMS FOR ELECTRONIC DATA PROCESSING EQUIPMENT [73] Assignee: Myler Digital Sciences, Inc.,

Maryland Heights, Mo.

[22] Filed: Jan. 29, I973 [21] Appl. No.: 327,780

Related US. Application Data [60] Division of Ser. No. 141,741, May 10, 1971, Pat. No.

3,735,366, which is a continuation-in-part of Ser. No. 876, Jan. 6, 1970, abandoned.

[52] [1.8. CI. 340/ 172.5, 340/324 M [51] Int. Cl. G061 3/14 [58] Field of Search 340/172.5, 324 AD, 324 M,

uncut? 01 MATIII 7/1971 Gardberg et a1 340/334 3,594,762 3,598.91 1 8/1971 Helbig 3,701,988 10/1972 Allaart 340/324 A Primary Examiner-Raulfe B. Zache Assistant Examiner-Mark Edward Nusbaum Attorney, Agent, or Firm-Robert .1. Schaap [57] ABSTRACT A display system for electronic data storage and retrieval equipment which permits the consecutive and intermittent display of information through a plurality of radiation active elements, such as cold cathode display tubes. The display system includes a recirculating main shift register which may form part of the data storage and retrieval equipment and which main shift register receives data bits representing characters to be displayed. A recirculating anode shift register is connected to the main shift register through a pulse divider and also receiver bits representing certain of the characters to be displayed. An anode driving circuit comprised of a plurality of anode drivers is operated in conjunction with the anode shift register and a plurality of cathode drivers are operated by a decoder connected to the main shift register. In this way a selected anode driver is energizable together with a cathode driver which will energize a selected one of said display tubes.

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DISPLAY SYSTEMS FOR ELECTRONIC DATA PROCESSING EQUIPMENT This application is a divisional application of our copending patent application, Ser. N0. M1 ,74 I, now US. Pat. No. 3,735,366 filed May 10, l97l, entitled Electronic Data Processing System" which is in turn a Continuation-ln-Part of application, Ser. No. 876, filed Jan. 6, I970, entitled Electronic Data Processing System (now abandoned).

BACKGROUND OF THE INVENTION This invention relates in general to certain new and useful improvements in electronic data processing systems, and more particularly, to a data storage and retrieval system which is capable of performing various arithmetic functions.

In recent years, there has been a widespread advance in data processing technology and an attendant introduction of commercially available data processing equipment. Many of these apparatus which have been characterized as desk model computers" are essentially reduced versions of the larger digital computing equipment. lnterestingly, these so-called desk model computers" are accurately characterized as computers since they are subject to a high purchase cost as well as a high operating cost which has notoriously accompanied the larger version digital computer.

Unfortunately, most of the research and development activities in the data processing area of technology have been concerned with increased speed of operation, reduction of component size, and increased versatility. While these research and development activities have resulted in the introduction of a large number of data processing equipment and has advanced the state of the art, the equipment can generally be acquired by only large organizations having sufficient capital to afford the cost of digital computing equipment.

Digital computing equipment of this type is generally beyond the need of most small business organizations as well as many of the medium-sized business organizations. Smaller business organizations typically do not require the wide degree of versatility which is available in much of the commercially offered digital computing equipment. Furthermore, and even more critical, the smaller business organizations can ill afford the purchase price or lease cost to obtain digital computing equipment as well as the substantial cost of operating such equipment. Moreover, most of the commercially available digital computing equipment requires the employment of programming or so-called software" for proper operation of the equipment. The need for this software imposes an additional financial burden on the small business organization which may be required to obtain the services of a programmer. Furthermore, each change in operating procedure of the business may well necessitate the change in the computer program to conform to the present business practices, and this. in turn, necessitates the revision of the software.

Many small business organizations which could well use the facilities of digital computing equipment such as in inventory control or simple data storage and retrieval, have found that the commercially available digital computing equipment was not economically feasible for employment. Accordingly, many of the business organizations which could effectively employ electronic data systems have continued to use the wellknown manual recordkeeping systems.

The system of the present invention is quite unique in that it serves as a means of storing and retrieving information on a real-time basis. In problems such as inventory control and the like, organizations have relied on commercially available digital computing equipment. The extant computing equipment is quite costly, not only in terms of the actual purchase or lease cost, but in the attendant requirements for programming personnel, keypunch personnel and skilled operators as well. The system of the present invention resides in two self-contained units which require no external programming and is designed to be operated by personnel relatively unskilled in the computer arts. In addition, since the claimed system does not require external programming, the design and construction is relatively simplified when compared to extant digital computing equipment and hence the cost of such system is materially reduced.

The system of the present invention is capable of having information introduced for further processing by direct key actuation and hence is capable of handling this information on a real time basis. The commercially available digital computing systems would require programmed inputs such as by punched cards or recorded magnetic tape, thereby effectively eliminating the feasibility of handling information on a real time basis. F urthermore, with the extant systems, the information to be processed must be converted to a proper predetermined format for computer acceptance. Since the system of the present invention is designed for direct key actuation, no special information encoding problems are encountered.

It is, therefore, the primary object of the present invention to provide an electronic data processing system which is capable of performing data storage and retrieval functions as well as performing the various arithmetic functions on the stored data.

it is another object of the present invention to provide an electronic data processing system of the type stated which is constructed in such manner that it can be effectively operated without the need of programming.

It is a further object of the present invention to provide an electronic data processing system of the type stated which effectively serves as a small digital computer for purposes of inventory control, stored credit information, and the like, and which is capable of highly efficient and accurate operation.

It is also an object of the present invention to provide an electronic data processing system of the type stated which can be manufactured substantially on a massproduction basis at a relatively low unit cost, thereby enabling the purchase of such equipment by relatively small business organizations.

With the above and other objects in view, our invention resides in the novel features of form, construction, arrangement and combination of parts presently de' scribed and pointed out in the claims.

FIGURES In the accompanying drawings (12 sheets): FIG. I is a perspective view of console unit forming part of an electronic data processing apparatus constructed in accordance with and embodying the present invention;

FIGS. 2a and 2b are composite schematic views illustrating the various components forming part of the electronic data processing apparatus, of which;

FIG. 2a is a schematic view of the electrical circuitry of the console unit forming part of the apparatus of FIG. 1;

FIG. 2b is a schematic view of a central electronics unit forming part of the electronic data processing apparatus;

FIG. 3 is a schematic view of the electrical circuitry employed when multiple console units are interfaced with a single central electronics unit;

FIG. 4 is a top plan view of the control panel forming part of a console unit of a modified form of electronic data processing apparatus constructed in accordance with and embodying the present invention;

FIGS. 5A, SB. 5C and 5D are composite schematic views illustrating the various components forming part of the modified form of electronic data processing apparatus, of which;

FIGS. 5A. 5B and SC are a schematic view of the electrical circuitry of the console unit forming part of the apparatus of FIG. 4;

FIG. 5D is a schematic view of a central electronics unit forming part of the modified form of electronic data processing apparatus;

FIG. 6 is a schematic view of the electrical circuitry employed when multiple console units of FIGS. 5A, 5B and 5C are interfaced with a single central electronics unit of FIG. 5D;

FIG. 7 is a schematic illustration of a magnetic drum or disc addressing scheme employed in the present invention;

FIG. 8 is a schematic illustration of a modified form of magnetic disc or drum addressing scheme employed in the present invention;

FIG. 9 is a composite diagramatic view consisting of FIGS. 9A-9H and showing the temporal relationship of clocking and data pulses used in high speed data transfer in the present invention, of which:

FIG. 9A illustrates a series of three clock pulses as they leave the central electronics unit;

FIG. 98 illustrates the series of the same three clock pulses as they are received in temporal relationship at the console unit;

FIG. 9C illustrates the series of the same three clock pulses as they clock data back to the central electronics unit in temporal relationship;

FIG. 90 illustrates a pair of l data pulses and the desired temporal relationship in which they should be received at the central electronics unit from the console unit;

FIG. 9E illustrates the same pair of l data pulses and the timing relationship with respect to the clock pulses in which the data pulses are actually received at the central electronics units after long cable transfer;

FIG. 9F illustrates a pair of early clock pulses as they leave the central electronics unit and their temporal relationship with respect to the normal clock pulses of FIG. 9A;

FIG. 9G illustrates a l data pulse and the timing relationship with respect to the clock pulses in which the data pulse is received at the central electronics unit with employment of early clock pulses;

FIG. 9H illustrates an offset in the timing of the data pulse so that it is received at the central electronics unit in such fashion that the clock pulse starts one half the time length of a data pulse later;

FIG. 10 is a composite view consisting of FIGS. l0Al0I and showing the temporal relationship of data pulses in such fashion that two sources cannot write in the same sector at the same time;

FIG. 11 is a schematic view of a 54 bit sector showing a portion of the sector reserved for arithmetic data and a portion of the sector reserved for accumulated data; and

FIG. 12 is a schematic view of an optional electrical circuit which can be used for both major display tubes and minor display tubes.

DEFINITIONS The recent advances in the field of cybernetics and more particularly in the field of data processing has created a condition of multiple uses of terms which has led to some confusion. In view of the fact that there is no accurate standardization of terms, the following definitions are set forth for purposes of clarity. It should be recognized that these definitions are only exemplary and, therefore, non-limiting.

As used herein:

Character a conventional or nonconventional mark, symbol, number or digit such as a decimal digit or letter of the alphabet or similar indicia.

Word one or more characters such as a group of decimal digits to fomi a number, as for example, ten decimal digits may represent one word.

Bit a binary element of a digital code where a group of binary elements may represent a decimal digit or arabic or other character and which is generated through conversion of a character to another type of character system or language; as for example, for bits generated from a decimal digit.

Reading the process of discerning and acquiring data from a member (the term reading is generally applied in digital arts and the term reproducing" is generally applied in analog arts, but have synonomous meanings herein).

Recording the process of registering data in some temporary, permanent or semipermanent form (the term recording is generally applied in analog arts and the term writing is generally applied in digital arts, but have synonomous meanings herein).

Sector a space or location in a magnetic storage member, such as disc or drum, reserved for recording of a predetermined number of bits, as for example, a nine character alphanumeric 6-bit code sector would contain 54 bit spaces.

Direct Addressing a process for recording a word or a portion thereof in a magnetic memory, or retrieving such word or portion thereof from such memory through defining the location, or by defining the sectors of the memory which define such location, of such word or portion thereof by directly recording bit combinations representing such word or words or portions thereof in a particular address location, or extracting the information therefrom by defining the bit combinations representing the location of such word or words in that particular address location.

Associative Addressing a process for recording a word or portion thereof in a magnetic memory, or retrieving such word or portion thereof from such memory through defining the location, or by defining the sectors of the memory which define such location, of such word or portion thereof by recording bit combinations unique for each sector of the memory in order to acquire a pre-recorded address and comparing such pre-recorded address during each word time with the desired address and selecting such desired address upon coincidence of comparison between the prerecorded address and the desired address.

Combination Associative-Direct Addressing a process for recording a word having a locator portion and a descriptor portion or a group of words with a locator portion and a descriptor portion in a magnetic memory, or retrieving such word or words from such memory by serially recording bit combinations for a locator portion in a particular location of one sector of the memory thereby defining a locator address, and recording bit combinations for a descriptor portion in a particular location of another sector of the memory and which location of the descriptor portion is related to the locator portion in addressable manner thereby defining a descriptor address; and retrieving such word or words by associatively selecting the locator address of the locator and directly selecting the descriptor address from the locator address.

The remaining terms used herein are deemed to have their commonly accepted art recognized meanings.

The term data is used in this specification refers to information in general and also refers to a sector of data which is associated with a part number address. However, in the included claims, the term data" is used in the generic sense to represent information in any intelligible code and is not limited to sectors of data representing information about any part number or address.

GENERAL DESCRIPTION Generally speaking, the present invention provides a system comprising both an apparatus and a method for achieving data storage and retrieval and performing certain arithmetic functions upon such data. Two embodiments of such apparatus and method which operates on a modified associative addressing principle are disclosed. The first of these embodiments employs a system which is capable of handling numeric data, and the second of these embodiments employs a system which is capable of handling alpha-numeric data. Systems for interfacing a plurality of console units to one central electronics unit is also provided. In another mode of operation the system of the present invention operates on the basis of a modified form of combination associative addressing and direct addressing.

The first embodiment of the apparatus includes two principal units, namely a console unit and a central electronics unit. The console unit contains a keyboard having the digits l-9, O and space. The other major components in the console unit include a multipurpose display shift register and parallel entry gates for entering information from the keyboard into the display shift register. A combination of an anode shift register along with anode drivers and cathode drivers operate a bank of display tubes such as cold cathode display tubes. These tubes each contain ten numerals, 19 and 0, so that upon proper energization, they are capable of displaying any of the ten numerals, 0-9. In a deenergized state, the tubes represent a space" condition. A divide by four counter as well as a BDC to line decoder is provided in order to circulate pulses through the display tubes.

The operators panel or so-ca1led control panel of the console unit includes, in addition to the keyboard, a clear switch which is capable of introducing a blank or space code into the display shift register. In addition, the operators panel includes a read" pushbutton switch, a write data pushbutton switch, a write part number switch, and an enable switch. The write data switch and the write part number switch are connected to and controllable by the enable switch so that the former two switches cannot be actuated without actuating the enable switch. The read switch is connected in such manner that it is capable of reading data from the memory section. The write data switch is connected in such manner that it is capable of introducing part data into the memory section. In like manner, the write part number switch is connected in such manner that it is capable of writing part numbers in the memory section.

Also mounted on the control panel is a digit change switch which is associated with each of the nine display tubes, and accordingly nine digit change switches are provided. In addition, a two-decade thumbwheel digit switch is also mounted on the operators panel in order to provide for adding and subtracting data. In like manner, an add pushbutton switch and a subtract pushbutton switch are mounted on the operators panel and are also connected to the enable switch. In this manner, the enable switch must be actuated before either an add or subtract function can take place. The console unit also includes an enter shift register which is operable with the digit decode, the parallel entry gates and the display shift register. Furthennore, the console unit includes a parallel to serial converter and a delay multivibrator, for reasons which will presently more fully appear.

The second principal unit serves as a combination central electronics-memory unit and which includes a memory section and an electronics section. The memory section generally comprises a magnetic drum hav ing a series of circuits which are operable with the drum; such as a sector clock amplifier, a write clock amplifier, an index amplifier, a data clock amplifier, etc. The drum is similar to conventional magnetic drums normally used in digital computing equipment and has a plurality magnetic record/reproduce heads for reading and writing on each track of the drum and which heads are connected to a write enable circuit and an NRZ input circuit. In addition, a track counter is provided for selectively enabling the reading of the next adjacent track after one track has been scanned.

The central electronics unit includes a read sequencer which is connected to the read switch on the control panel and to the clear switch on the control panel. The central electronics unit also includes a write sequencer which is connected to the write data switch and the write part number switch. The central electronics unit additionally includes a serial BCD adder/subtractor which is connected to the display shift register as well as the add/subtract functions in the console unit. This adder/subtractor is capable of performing the various arithmetic functions capable of being accomplished by this apparatus. A search shift register is also located in the central electronics and which is operable by two sets of gates, the first of which is connected to the read sequencer and the second of which is connected to a valid data detector and a preamble oneshot. A bit counter is connected to the search shift register through the first set of gates. Additional components, such as clock switches, a preamble register, a sector count module, and data flip-flops are also included in the central electronics unit.

A series of transmitters and receivers are interposed between the console unit and the central electronicsmemory unit. The transmitters are generally low impedance drivers capable of supplying sufficient current to drive the line with which it is associated when the line is loaded with its characteristic impedance. The receivers employed are generally matched impedance differential amplifiers with proper logic level outputs.

The central electronics section provides control of the memory section under direction of the various switches on the control panel. Furthermore, the addition and subtraction is performed in the central electronics unit in the manner as previously described. Power supplies may be properly installed in the central electronics unit to provide the operating voltages necessary for the control console, the various components in the central electronics unit as well as the memory section which includes its own input/output electronics.

Actuation of the clear switch on the control panel assures the clearing of any remaining or extraneous data in the electronics unit. When it is desired to enter a new part number into the memory section, the part number representing an available part number position in the memory section is introduced by proper actuation of the keyboard to place the numbers representing this available position in the display shift register. This same number will also appear on the display tubes. The read switch is actuated to search for and acquire this part number position which is again displayed on the display tubes. The keys of the keyboard are again actuated to introduce a desired new part number and the write part number switch is then pressed after being enabled by the enable switch so that this new part number may be entered into the memory section. The part data associated with the new part number is also entered by way of the keyboard and, furthermore, the part number and part data are displayed on the control console for examination of accuracy prior to recording in the memory section.

A four bit BCD code is used to represent one integer of the decimal system. For a 9 integer part number, a sector of 36 bits is used to represent the 9 decimal digit part number. This initial 36 bits representative of the part number is followed by an additional sector of 36 bits which provides part data relating to that part number. Accordingly, an associative type of addressing is employed, in that, data relating to a particular part number is recorded in the memory section by reference to the part number.

If it is desired to change a particular part number, the part number is introduced into the display shift register by means of the keyboard. In the present invention, the particular part number is a locator and could represent a name, account number of the like. The concept of part number and part data" associated with the part number is more fully described in detail hereinafter. The read button is actuated so that a search for this part number may be initiated. This search will occur in the search shift register by comparing the addressed part numbers in the memory section with the part number which has been introduced into the display shift register. The new part number is then introduced into the display shift register by way of the keyboard. In like manner, part data associated with the new part number may also be introduced into the apparatus. The write part number switch is actuated to introduce the part number into the memory section. Furthermore, the write data switch is actuated after introduction of the part data into the display shift register for recording this part data in the memory section. Comparison is then performed with information contained in the memory section.

During the search of the memory section, information on successive tracks of the drum is compared with the part number introduced into the display shift register and ultimately transferred to the search shift register. The output of the search shift register and the information read from the memory section are compared in a comparator circuit. Correlation of address information present in the search shift register with corresponding address information from the drum enables the comparator circuit to generate an output which is anded with a sector clock output causing the display shift register to retain the subsequent sector of data. The desired data word is stored in the display shift register and caused to be illustrated by the display shift register.

If it is desired to change the data associated with a particular part number, the part number which has been previously stored in the memory section is found in the manner as previously described by introducing the number into the display shift register and finding comparison with the addressed part number through the search shift register.

Arithmetic functions can be performed through the use of the thumbwheel switches provided on the control panel. For example, if it is desired to subtract a number from a portion of the data digit, this number is introduced by means of the thumbwheel switches. The subtract switch on the control panel is actuated for entering a BCD equivalent of the decimal digits to be subtracted. Subtraction of these decimal digits from the data is then performed and the difference is recorded in the memory section. After the recording is completed, the data is received from the memory section and sent to the display tubes through the display shift register for examination. Addition may be performed in a similar fashion except that the add switch on the control panel is actuated in place of the subtract switch.

An alternate means of changing the data associated with a part number is by use of nine pushbuttonoperated change digit switches which are located beneath each of the nine display tubes. For this method, the subject part number is entered into the search shift register, and the disc location is determined as ex plained above. The data thus displayed may be altered by simultaneously depressing the change digit pushbutton switch located beneath the digit to be changed, and the desired keyboard key. The digit then changes to the keyboard numeral. This process is repeated for the remaining digits requiring alteration. When'the desired digit changes have been made, the new information is entered into the memory by actuating the write data switch.

It is possible to connect a plurality of console units to one central electronics unit so that each of the console units are individually capable of receiving data from the central electronics unit as well as adding and subtracting to the part data contained in the memory section of the central electronics unit. In this system, the switch circuits of each of the console units, namely the read circuit, the write data circuit, the write part number circuit, the subtract circuit and the add circuit are connected to an OR gate structure. In addition, console data and add-subtract data from each console unit are connected to the OR gate structure, which is in turn connected to the central electronics unit. Each of the console units receive memory data and memory clock pulses from the central electronics without interposition of the OR gating structure.

This system also employs a console switching circuit which receives transfer information from the console and provides data transfer information to each of the consoles. Furthermore, a console inhibit circuit is employed which receives clear pulses from each of the console units and a busy signal pulse from the console switching circuit. The console units are arranged in such a manner that the console data and add and subtract data are all zeroes except when data transfer is initiated. Actuation of any of the switch circuits on any particular console unit will inhibit any other console unit from operating the central electronics unit until the clear switch on the console unit accessing the central electronics unit has been actuated. Actuation of the clear switch on the last named console unit will release the control switching circuit and thereby enable other console units to access the central electronics unit.

An apparatus of the present invention is also capable of handling alphanumeric data and also contains two major units, namely a console unit and a central electronics unit. The console unit of the alpha-numeric apparatus is capable of handling 40 distinct characters which may be introduced by keyboard and is transferred to a six bit encoder for generating six bits for each character introduced into the apparatus. The console unit also includes a 54 bit console register which similarly serves a plurality of functions. In addition, the console unit is capable of introducing data to perform arithmetic functions such as addition and subtraction. A read switch and write data switch are also employed in the same manner as the numeric apparatus. For purposes of performing the addition and subtraction, an add switch and subtract switch are provided. A twodecade thumbwheel digit switch is also provided in order to introduce the data to be subtracted from or added to part number data.

The console unit of the alpha-numeric apparatus includes a write part number switch as well as a change part number switch. In the numeric apparatus, an adress in which a new part number could be entered was located by searching for an all zero address. The alpha-numeric apparatus is provided with a zeroes locator which automatically searches the memory section for an empty address sector. The console unit also includes a space code generator which is capable of generating spaces in the console register upon actuation of a clear switch. Furthermore, the console unit includes nine display tubes which may be energized for visually displaying in alpha-numeric format, the bit information which is contained in the console register. Actuation of the clear switch introduces all spaces into the console register as previously described. Accordingly, writing of part data or part numbers into the console register actually causes a writing over the spaces. It should be recognized that the space which is introduced in the form of a six bit byte is recognized by the memory section as six bits and is as valid to the memory section as any other byte of six informational bits. However, since the alpha-numeric unit operates on a six bit basis, these bits are decoded on the output of the console register into a 13 bit data format in order to energize l3 segment display tubes. These segments in the display tubes will form the various characters in alpha-numeric form for display purposes. The alphanumeric apparatus also employs an anode register along with the six bit to 13 segment decode circuit in order to energize selected display tubes.

The console unit also includes a comparator circuit which is connected to the zeroes locator for selecting a proper sector in the memory section in which a part number can be written. Furthermore, the console unit includes a sector counter operable with a part number/'- part data flip-flop. In addition, the console unit includes a write sequencer and a read sequencer.

The alpha-numeric apparatus of the present invention operates on the basis of a combination associative and direct addressing principle. As indicated previously, when it is desired to introduce a new part number into the memory section, an all zeroes sector of the memory is located and the part number is introduced into this all zeroes sector. When it is desired to reacquire this part number and/or the data associated therewith, the part number is introduced into the console unit by means of the keyboard and an associative search of the memory section is performed until the then recorded part number is located. The part data is directly addressable with respect to the part number. The data may be recorded in the same track of the drum and in a sector of this track which is related in time and space to the part number.

In a preferred embodiment of the present invention, the part data is preferably located in a track which differs from the track containing the part numbers. For this purpose, the console unit is provided with a change track sequencer. The change track sequencer in the console unit will command a track jump operation to the central electronics unit at a prescribed time. In essence, when the associative search reveals the part number, the change track sequencer will cause the central electronics to select the read head for an adjacent track in order to acquire the data associated with the particular part number. Again the data is located in both a predetennined time and distance relationship with respect to the part number. Thus, if the data is located in the next adjacent track to the track containing the part number, the data is generally located two sectors after the part number in such adjacent track.

The console unit also includes a redundant address inhibit circuit which prevents the same part number address from being recorded twice in the memory section. In addition, the console unit also includes an early clock sequencer which sends out clock pulses on a basis to introduce information to and from the memory section on a proper time basis. When high speed transfers over long transfer lines is involved, the data from the console unit may arrive at the memory section at a time equivalent to several clock pulses later than the time in which the data should arrive. The early clock system of the present invention obviates this problem. The remainder of the operation of the console unit is somewhat similar to the operation of the console unit in the numeric apparatus.

The electronics unit in the alpha-numeric apparatus differs somewhat from the electronics unit in the numeric apparatus. In the alpha-numeric apparatus, the memory address register is no longer employed. The console register maintains its own addressing function. Furthermore, when a plurality of console units are employed, each individual console unit is capable of reading simultaneously to search for its own address. In the numeric apparatus, data transfer signals were received in the console unit from the read and the write sequencers which enabled the console to transmit data. In the alpha-numeric apparatus, the central electronics unit sends data to the console unit at all times, except during portions of a write operation. However, in each of the apparatus, sector clock pulses are received only from the memory section of the electronics unit.

The electronics unit also includes the major components such as a serial BCD adder/subtracter and a nines complement generator, the latter enabling subtraction functions. In addition, the preamble register is provided for adding a preamble and postamble to the part numbers and part data to be written on the drum, The circuitry of the central electronics unit is materially simplified in the alpha-numeric apparatus.

When it is desired to read a part number included in the memory section or to read the part data associated with that part number in the memory section, the part number is introduced into the console register by means of the keyboard. Read information has been continually received by the console unit at all times. Accordingly, when the read switch is actuated, comparison with part numbers in the memory section can be made serially on a bit-by-bit basis. Information from the console register is transmitted into the comparator for this comparison function. A comparison will exist only at sector time and if comparison did exist, then it is apparent that the next sector in sequence contains part data associated with the part number. A modulo r1557 counter (where n is the number of tracks on the drum) is provided to retain the drum location from which the part data was removed. The counter is initialized on each count of n55? in order to determine the address of this particular sector of part data. The part data information is then introduced into the console and is circulated six bits at a time.

To change a part number, the existing part number is introduced into the console register by means of the keyboard. The change part number switch is then actuated and this, in turn, will deenergize the display during the searching for the existing part number. After the part number is found from the memory section, the sector counter is set. At this time, the display tubes remain extinguished. A new part number is then introduced by means of the keyboard and the change part number button is again actuated. This latter operation automatically enters the new part number on the drum using the sector counter to determine the proper drum location. In order to write a new part number, the number is introduced and the write new part number switch is actuated. The zeroes locator serves to select a part number location with all zeroes and the part number is subsequently recorded in this location. The part data/- part number flip-flop essentially keeps track of the sectors which contain part numbers and the sectors which contain part data. The central electronics unit of the alpha-numeric apparatus also includes a track jump sequencer which operates in conjunction with the change track sequencer of the console unit. These two sequencers in combination enable the unique combination associative-direct addressing system used in the present invention. An accumulated data sequencer and an accumulated data storage register is also included in the central electronics unit for the purposes of accumulating certain of the data included in the data sectors over periodic time intervals.

The present invention also provides a circuit for employing a plurality of alpha-numeric console units with one central electronics unit. This system includes a gating structure for introducing add-subtract data, console data, write and add/subtract functions into a central electronics unit. Outputs from the central electronics unit which include sector clock pulses, index clock pulses, read clock pulses, write clock pulses and memory data are all transmitted simultaneously to the various console units.

DETAILED DESCRIPTION OF A NUMERIC DATA SYSTEM Referring now in more detail and by reference characters to the drawings which illustrate practical embodiments of the present invention, A designates an electronic data processing apparatus which generally comprises a console unit C and a central electronics unit E which includes a memory section M. The console unit C which is illustrated in FIG. 2A is provided for removable attachment and connection to the central electronics unit E, the latter being illustrated in FIG. 28. It can thus be seen that terminal connectors may be provided on the console unit which may be located in a separate housing from the central electronics unit E for attachment to a like terminal on the central electronics unit E. Accordingly, it can be seen that a plurality of console units C can be conveniently connected to one central electronics unit E. In like manner, it should be observed that both the console unit C and the central electronics unit E can be conveniently mounted in one housing as a unitary assembly.

The console unit C, which is functionally illustrated in FIG. 2A, generally comprises an outer housing 1, which is provided with an upwardly inclined control panel 2 and a somewhat vertically located display panel 3, in the manner as illustrated in FIG. 1. The housing may be provided with removable closure plates (not shown) for providing access to the interior thereof, or the housing may be disposed upon and shiftable with respect to a base plate. Any suitable lightweight metal or moldable plastic material may be used in formation of the housing I. The display panel 3 is cut away in the provision of a display aperture 4 to accommodate nine or more cold cathode display tubes 5.

Located on the control panel 2 is a keyboard entry block 6 having 11 keys 7 labeled 0 and 1 through 9 and space for purposes of introducing information such as part numbers and part data into the apparatus A. A suitable switch (not shown) which may form part of, or may be associated with each key 7 is connected to a diode matrix 8 which generally has a series of diodes connected in such fashion as to generate a BCD code equivalent to a decimal digit system. Accordingly, actuation of any one of the keys 7 representing a decimal digit will cause the generation of 4 bits in the BCD code to represent that decimal digit. The diode matrix 8 which is used for generating the BCD code is well within the design purview of the skilled artisan and is therefore neither illustrated nor described in any furter detail herein.

A "clear switch 9, a read switch 10, and add" switch 11, a subtract" switch 12, a write part number" switch 13, a write data" switch 14, and an enable" switch are all mounted on the control panel 2 in the manner as illustrated in FIG. 1. Each of these aforesaid switches, with the exception of the enable switch 15, are pushbutton switches and are capable of being pressed for actuation and which are biased to return to the deactuated condition. The enable switch 15 is an alternate action type switch and is operatively connected to the write part number switch 13, the write data switch 14, as well as the add switch 11, and the subtract switch 12 in order to enable actuation of these latter four switches in a manner to be described hereinafter. Thus, in order to actuate any of the four aforesaid switches, it is first necessary to actuate the enable switch 15. The various switches 9-15 all internally contain lights, such as small conventional incandescent bulbs so that the face of the switch will be lightdisplayed when the switch is ready for actuation. When the enable switch 15 is actuated and illuminated, the other switches such as the add switch 11, the subtract switch 12, the write part number switch 13, and the write data switch 14 are illuminated and may be actuated.

By further reference to FIG. 2A, it can be seen that the diode matrix 8 is provided with four exit lines 16 which are connected to parallel entry gates 17 and one line 18 which is connected to a delay 19 such as a oneshot. The four entry lines 16 are labeled one, two," four, and eight, which is representative of the BCD code bits transmitted to the parallel entry gates 17. The clear switch 9 also is connected along with the two" and eight entry lines 16 to the parallel entry gates 17 through OR gates 18 in the manner as illustrated. The clear switch 9 employs a slightly modified form of BCD code, which uses a blank data position. For example, a BCD code of eight, four, two, one would have a blank position represented by 1010.

The parallel entry gates 17 are connected to a display shift register 20 by means of eight transference lines in the manner as illustrated in FIG. 2A. It should also be observed that the clear switch 9, keyboard 6, the read switch 11, the write data switch 14, the write part number switch 13, the enable switch 15, the add switch 1] and the subtract switch 12 are all available for operation inputs. The display shift register 20 is a circulating shift register and serves at least three major functions which are described hereinafter in more detail. The shift register 20 contains 36 serially connected bistable multivibrators (flip-flops) 21 so that the shift register 20 is capable of holding 36 bits of information at any point in time.

As indicated previously, information in decimal digit form is introduced into the apparatus through the keyboard 6 in BCD format. Actually, the apparatus is capable of handling information about a particular item such as a part number, and additional information, eg part data, regarding that part number. Accordingly, a first sector of 36 bits is generated to identify a particular part number. An additional sector of 36 bits is also generated and this latter sector includes a part data information about that part number.

The term part number as used herein represents a sector of a known number of bits, e.g. for the numeric apparatus 36 bits, and for the alpha-numeric apparatus 54 bits, and which sector of bits contains information identifying a particular good, item. service, or other element capable of being identified and addressed. However, the presently described embodiments of the present invention refers to such identified and addressed element as a "part number.

The term part data as used herein represents a sector of a known number of bits, e.g. for the numeric apparatus 36 bits, and for the alpha-numeric apparatus 54 bits, and which sector of bits contains information relating to a part number identified by the preceding sector of a known number of part number bits. The term data" is used in its generic sense to represent a sector of a known number of bits, e.g. for the numeric apparatus 36 bits, and for the alpha-numeric apparatus 54 bits, and which bit contains useful information. Accordingly, a data" sector of bits may represent a part number, part data or other allied information.

It should be recognized that while the present invention has been described in terms of apparatus for storing part numbers and respective data about those part numbers, that other types of information could be stored as well. For example, the first 36 bits could be used to represent an account number such as a credit card account number. The additional sector of 36 bits would then provide information about that particular account number. However, for purposes of illustrating and describing the present invention, the apparatus will be described in terms of storing and operating upon part numbers and part data associated with such part numbers. Naturally, if other types of information is to be stored, the nomenclature on the various pushbutton switches located on the control panel 2 would be altered accordingly.

For example, it could be assumed that the second sector of 36 bits representing part data about a part number (9 decimal digits representing part data about the part number) will include 3 decimal digit positions for providing inventory quantity. The last 3 decimal digits of the decimal digit information, which is the least significant 3 digits, will represent such inventory data. The other 6 decimal digit positions can then be used in coded form to represent the name of the particular supplier, price, or location of the inventory, etc.

The output of the clear switch 9 is connected to one input of the parallel entry gates 17 and another input to the parallel entry gates 17 is received from an AND gate 22, the latter also having an input from the delay 19. Furthermore, the output of the clear switch 9 is connected in OR fashion with the 2 and 8 input lines 16 from the diode matrix 8 to the parallel entry gates 17 in the manner as previously described. The output of the display shift register 20 is connected to a plurality of serial gates 23, the output of which is. in turn, connected to the input of the display shift register 20 in order to enable recirculation through the display shift register 20.

The console unit C also includes an anode shift register 24 having 9 serially connected flip-flops 25. The anode shift register 24 is provided with 9 output lines which are connected to the inputs of 9 anode drivers 26 forming part of an anode driving circuit 27. The output of each flip-flop 25 in the anode shift register 24 is individually connected to a single anode driver 26 in the 

1. A system for enabling consecutive intermittent display of information through a plurality of radiation active elements and where said radiation active elements have first terminals and second terminals; said system comprising a register having a plurality of multistable elements, input means operatively associated with said register to introduce a plurality of bits representative of a plurality of indicia into said register and where a byte comprised of a selected number of said bits is representative of one of said plurality of indicia, anode energizable means operatively connected to the first terminal of each said radiation active element, cathode energizable means operatively connected to the second terminal of each said radiation active element, means operatively associated with said register to enable recirculation therein of the bits contained in said register, selector means operatively connected to said register and said anode energizable means and said cathode energizable means to cause energization of selected ones of said radiation active elements when a selected byte of bits is introduced from said input means and into a selected group of multistable elements in said register, the number of multistable elements in said selected group of multistable elements being equal to the number of bits in said selected byte, and shifting means operatively associated with said register to periodically shift the bits contained therein to said selected group of multistable elements, said shifting means also being operatively assocated with said selector means to cause the selector means to intermittently display the radiation active elements on a consequtive basis as the bits in said register are introduced into said selected group of multistable elements.
 2. The system of claim 1 further characterized in that timing means is operatively connected to said register for controlling the time that any selected ones of said radiation active elements remains energized.
 3. The system of claim 1 further characterized in that said register is a recirculating shift register and that said multistable elements are bistable multivibrators.
 4. The system of claim 1 further characterized in that said anode energizable means comprises a plurality of anode drivers, the number of which is equal to the number of radiation active elements capable of being energized, and said cathode energizable means comprises a plurality of cathode drivers, the number of which is equal to the number of second terminals of each radiation active element capable of being energized.
 5. The system of claim 4 further characterized in that the number of bytes capable of being held in said register is equal to the number of radiation active elements capable of being energized.
 6. The system of claim 1 further characterized in that said anode energizable means comprises a plurality of anode drivers, the number of which is equal to the number of radiation active elements capable of being energized, and said cathode energizable means comprises a plurality of cathode drivers, the number of which is equal to the number of second terminals of each radiation active element capable of being energized, said selector means comprising an anode shift register operatively connected to said anode drivers, and a decoder operatively connected to said register and said cathode drivers.
 7. The system of claim 1 further characterized in that said anode energizable means comprises a plurality of anode drivers, the number of which is equal to the number of radiation active elements capable of being energized, and said cathode energizable means comprises a plurality of cathode drivers, the number of which is equal to the number of second terminals of radiation active elements capable of being energized, said selector means comprises an anode shift register operatively connected to said anode drivers, a pulse divider to divide the number of bits contained in each plurality of indicia by the number of bits contained in each byte and being connected to said anode shift register for energizing a selected one of said anode drivers, a decoder operatively connected to said register and said cathode drivers and being capable of producing a number of pulses at least equal to the number of second terminals of radiation active elements for each byte so that a selected anode driver which is energizable together with a cathode driver will energize a selected one of said radiation active elements.
 8. The sytem of claim 2 further characterized in that the timing means is a delay multivibrator.
 9. A system for enabling display of characters in a first bank of a plurality of individual radiation emitting elements and a second bank of a plurality of individual radiation emitting elements associated with a data storage and retrieval apparatus so as to display characters introduced into and retrieved from said data storage and retrieval apparatus; said system comprising first register means operatively connected to said first bank of radiation emitting elements and receiving bits of a digital code representing a first type of character, second register means operatively connected to said second bank of radiation emitting elements for receiving bits of a digital code representing a second type of character, and where said first type of character is different than said second type of character, selection means operatively connected to said first register means and to said second register means, said selection means operatively determining the bits representing said first type of character and permitting introduction of the bits representing said first type of character into said first register means, said selection means also operatively determining the bits representing said second type of character and permitting introduction of the bits representing said second type of character into said second register means, energization means enabling selected ones of the individual radiation emitting elements in said first and second banks to be energized for display of characters according to and corresponding to the bits respectively introduced into said first and second register means, and means operatively connected to said energization means for consecutively energizing the radiation emitting elements of said first bank and consecutively energizing the radiation emitting elements of said second bank.
 10. The system of claim 9 further characterized in that said radiation emitting elements have a plurality of terminals, first anode and cathode energizable means operatively connected to said plurality of terminals of said radiation emitting elements of said first bank, and second anode and cathode energizable means operatively connected to said plurality of terminals of said radiation emitting elements of said second bank.
 11. The system of claim 10 further characterized in that means is operatively connected to said energization means for consecutively and intermittently energizing the radiation emitting elements of said first bank and consecutively and intermittently energizing the radiation emitting elements of said second bank.
 12. The system of claim 9 further characterized in that the first type of character is an arabic character, said first register means includes elements for receiving said bits representing said first type of character, that said second type of character is a numeric character, and said second register means includes elements for receiving the bits representing said second type of character.
 13. The method of consecutively and intermittently displaying information through a plurality of radiation active elements, said method comprising converting each informational character into a plurality of bits forming one byte which is representative of said informational character, introducing and storing the bits of a plurality of bytes in multistable elements of a main register, passing bits representing the characters to be displayed into an anode register, recirculating the bits contained in said anode register and selectively energizing the anode terminal of selected ones of said radiation active elements, selectively energizing the cathode terminals of the radiation active elements in which the anode terminals have been energized, selectively energizing selected ones of said radiation active elements when a selected byte of bits is introduced into a selected group of multi-stable element in said main register and which selected group of multi-stable elements is correlatable to the selected ones of said radiation active elements to be energized, controlling the time that any selected ones of said radiation active elements remain energized, and periodically shifting the bits contained in said main register to the selected group of multi-stable elements to intermittently display the radiation active elements on a consecutive basis as the bits in said main register are introduced into the selected group of multistable elements.
 14. The method of claim 13 further characterized in that the method comprises introducing into said main register a number of bytes equal to the number of radiation active elements capable of being energized.
 15. The method of claim 14 further characterized in that the method comprises selectively energizing a plurality of radiation active elements in a plurality of banks thereof.
 16. A system for enabling consecutive intermittent display of information through a plurality of radiation active elements and where said radiation active elements have first terminals and second terminals; said system comprising a main register having a plurality of multistable elements, input means operatively connected to said main register to introduce a plurality of bits representative of a plurality of indicia into said register and where a byte comprised of a selected number of said bits is representative of one of said plurality of indicia, anode energizable drivers operatively connected to the first terminals of said radiation active element, the number of anode energizable drivers being equal to the number of radiation active elements capable of being energized, a plurality of cathode energizable drivers operatively connected to the second terminals of said radiation active elements, the number of cathode energizable drivers being equal to the number of second terminals of the radiation active elements capable of being energized, selector means operatively connected to said register and said anode energizable drivers and said cathode energizable drivers to cause energization of selected ones of said radiation active elements when a selected byte of bits is introduced from said input means and into a selected group of multistable elements in said register, the number of multistable elements in said selected group is equal to the number of bits in said selected byte, an anode shift register operatively connected to said anode drivers, a pulse divider to divide the number of bits contained in each plurality of indicia by the number of bits contained in each byte and being connected to said anode shift register for energizing a selected one of said anode drivers, a decoder operatively connected to said main register and said cathode drivers and being capable of producing a number of pulses at least equal to the number of second terminals of radiation active elements for each byte so that a selected anode driver which is energizable together with a cathode driver will energize a selected one of said radiation active elements, timing means operatively connected to said main register member for controlling the time that any selected ones of said radiation active elements remains energized, and recirculation means operatively associated with said main register to periodically enable a shifting and recirculation of the bits contained in said main register to thereby periodically shift the bits contained in said register into said selected group of multistable elements, said selector means being operatively connected to said main register in such manner and being operatively associated with said recirculation means to cause the selector means to intermittently display the radiation active elements on a consecutive basis as the bits in said main register are introduced into the selected group of multistable elements.
 17. A system for enabling consecutive intermittent display of information through a plurality of radiation active elements and where said radiation active elements have first terminals and second terminals; said system comprising a register having a plurality of multistable elements, input means operatively associated with said register to introduce a plurality of bits representative of a plurality of indicia, the number of bytes capable of being held in said register being equal to the number of radiation active elements capable of being energized, anode energizable means operatively connected to the first terminal of each said radiation active element, cathode energizable means operatively connected to the second terminal of each said radiation active element, means operatively associated with said register to enable recirculation therein of the bits contained in said register, selector means operatively connected to said register and said anode energizable means and said cathode energizable means to cause energization of selected ones of said radiation active elements when a selected byte of bits is introduced from said input means into a selected group of multistable elements in said register, and shifting means operatively associated with said register to periodically shift the bits contained therein to said selected group of multistable elements, said shifting means also being operatively associated with said selector means to cause the selector means to intermittently display the radiation active elements on a consecutive basis as the bits in said register are introduced into said selected group of multistable elements.
 18. The system of claim 1 further characterized in that the number of multistable elements in said selected group of multistable elements is equal to the number of bits in said selected byte.
 19. The system of claim 17 further characterized in that said anode energizable means comprises a plurality of anode drivers, the number of which is equal to the number of radiation active elements capable of being energized, and said cathode energizable means comprises a plurality of cathode drivers, the number of which is equal to the number of second terminals of each radiation active element capable of being energized, said selector means comprising an anode shift register operatively connected to said anode drivers, and a decoder operatively connected to said anode drivers, and a decoder operatively connected to said register and said cathode drivers. 